IBIS Macromodel Task Group

Meeting date: 25 November 2008

Members (asterisk for those attending):
  Ambrish Varma, Cadence Design Systems
* Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Brad Brim, Sigrity
  Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
  Donald Telian, consultant
  Doug White, Cisco Systems
  Essaid Bensoudane, ST Microelectronics
  Fangyi Rao, Agilent
  Ganesh Narayanaswamy, ST Micro
  Gang Kang, Sigrity
  Hemant Shah, Cadence Design Systems
  Ian Dodd, Agilent
  Joe Abler, IBM
* John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Mike Steinberger, SiSoft
  Mustansir Fanaswalla, Xilinx
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
  Ray Comeau, Cadence Design Systems
  Richard Mellitz, Intel
  Richard Ward, Texas Instruments
  Sam Chitwood, Sigrity
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence Design Systems
  Sid Singh, Extreme Networks
  Stephen Scearce, Cisco Systems
  Steve Pytel, Ansoft
  Syed Huq, Cisco Systems
  Syed Sadeghi, ST Micro
  Terry Jernberg, Cadence Design Systems
  Todd Westerhoff, SiSoft
  Vikas Gupta, Xilinx
  Vuk Borich, Agilent
  Walter Katz, SiSoft
  Zhen Mu, Cadence Design Systems

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Opens:

- Mike L can not take minutes next week
  - Randy will take minutes

- Plans for upcoming meetings:
  - Some members may be unavailable at times in the mext month
  - We will meet Dec 2, 9, 16
  - There will be no meeting Dec 23 and 30

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Call for patent disclosure:

- No one declared a patent.

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Review of ARs:

- Michael M:  Send proposal document to Mike LaBonte for posting; also
	       confirm with Synopsys whether "used by permission" can be used as
	       the official indicator on relevant documents.
  - We have email permission from Synopsys
  - Synopsys was concerned over whether we have something finished
  - We will need formal documentation when our work comes to a vote
  - Michael M will check again, but we should be able to upload

- Arpad:  Write parameter passing syntax proposal (BIRD draft)
          for *-AMS models in IBIS that is consistent with the
          parameter passing syntax of the AMI models
          - TBD

- TBD:    Propose a parameter passing syntax for the SPICE
          - [External ...] also?
          - TBD

- Arpad:  Review the documentation (annotation) in the macro libraries.
          - Deferred until a demand arises or we have nothing else to do

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New Discussion:

Bob: Is the AMI software donation from SiSoft waiting for something?
- The conditions have not yet been agreed on
- We need to have a board meeting

Bob: If we add a B element to IBIS SPICE, is that still part of the agreement?
- Michael M: We only drove a single stake in the ground with Synopsys
  - Trying to avoid a catch-22
  - We should not set ourselves up for failure by letting the scope creep
   - We only discuss interconnect use with Synopsys
- Michael M showed the Goals and Scope page of the proposal
  - It does not mention the B element

Arpad: We may have to make limited improvements to C_comp
- Bob: Opposed to a major change in IBIS
  - We already abandoned a pole-zero approach
  - Michael M had proposed a ladder circuit approach
  - Walter's proposal would be a big jump just for C_comp
- Arpad: John had also proposed an approach
  - Walter's proposal is more far reaching
  - It moves a lot of content outside the IBIS file
  - What would be left for IBIS?

Michael M: We need an overhaul
- For RX IBIS only has pin lists with measurements
- The package model is insufficient
- The measurements is insufficient
- All that is left is a pin list
- Mike L: Plug and play is important
  - Michael M: Only in post-layout analysis
  - Arpad: More and more 1-buffer IBIS models are appearing (serdes)
- Arpad: Will the vendors who support IBIS go along with big changes
  - Michael M: They will follow their market segments
    - In some segments IBIS is dead
    - We need to identify the market segments
- Michael M: One user ended up using pure VerilogA for PCIX
  - For analog, AMI may be too complicated
- Arpad: Where does SPICE break down? Why turn to VerilogA?
- Michael M: IBIS was winning when it was seen as the only alternative to transistor SPICE
  - It was much faster
  - Adding new stuff to IBIS may be adding more complexity than alternatives
  - Flexible languages are open ended, but can be too complicated
    - It can be very hard to extract models
- Arpad: Is there a way to achieve freedom without complexity?
  - Bob: Only silicon vendors are able provide complex models
    - Someone has to be producing this as part of their job
- Radek: We need to consider how this affects VT tables
  - We have customers using existing IBIS files
  - Michael M's proposal for C_comp looks good enough
- Arpad: Personally, all these little changes reflect IBIS inflexibility
- Mike L: hat Bob is describing is reminescent of IMIC
  - Arpad: IMIC table models were for transistors

- We will discuss our direction next week
  - People should bring their lists of things that need to be solved

Next meeting: 02 December 2008 12:00pm PT

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